81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
Resource
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Journal
2004 IEEE International Solid-State Circuits Conference, 2004
Pages
-
Date Issued
2004-02
Date
2004-02
Author(s)
Fang, Hung-Chi
Huang, Chao-Tsung
Chang, Yu-Wei
Wang, Tu-Chih
Tseng, Po-Chih
Lian, Chung-Jr
DOI
0193-6530
Abstract
An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.
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Type
conference paper
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