A 2D Analysis for Capacitance Characteristics of Partially-Depleted SOI NMOS Devices
Date Issued
2004
Date
2004
Author(s)
Wang, Shan-Jie
DOI
zh-TW
Abstract
This thesis reports a 2D analytical simulation for the capacitance characteristics of partially-depleted (PD) silicon on insulator (SOI) NMOS devices.
In chapter 2, we make a brief description of the mechanism for kink effect of PD SOI NMOS devices and study the triggering VDS with the conditions in different operating temperature and different thin film dopping concentration.
In chapter 3, by using the 2D device simulator(Medici), we make a simulation of CDG,CSG,CGD,CGS versus VDS for different gate voltages. For the simulation results, we discuss and present some physical viewpoints.
Subjects
電流突增
電容特性
部分解離絕緣體上矽
kink effect
Capacitance Characteristics
PD SOI
Type
thesis
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