A Third-Order Multi-Bit Continuous-Time Delta-Sigma Modulator with Incremental Data Weighted Averaging
Date Issued
2007
Date
2007
Author(s)
Tsai, Ming-Chung
DOI
en-US
Abstract
Designed for a narrow-band application, a third-order multi-bit continuous-time delta-sigma modulator is presented in this thesis. In the modulator, the incremental data weighted averaging algorithm is employed. The IDWA can achieve first-order DAC noise shaping and move the signal dependent tone out of the signal band. This delta-sigma modulator is implemented in the TSMC 0.18-μm COMS process. The proposed modulator achieves a 77-dB peak SNR with a 100-kHz bandwidth at a 24-MHz sampling rate and has an 80-dB dynamic range. The implemented modulator dissipates only 4.5 mW from a 1.8-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless zero-IF or low-IF receiver systems.
A low-voltage low-power CMOS OTA is also introduced in this thesis. The proposed circuit is based on the current-mirror topology. To circumvent the low-gain problem of a CMOTA, several design techniques are employed. First, the output impedance is increased by reducing the bias currents of the output branches, which is realized by shunting partial mirror currents away. These shunt currents are then reused to realize the second input stage. In addition, body terminals are utilized as inputs to augment the transconductance. Finally, the class-AB output stage further enhances the gain. The proposed OTA is implemented in the TSMC 0.18-μm COMS process. With a load 16.8 pF, the proposed OTA achieves a 55-dB gain at 30 kHz with a unity-gain frequency of 26.3 MHz and the phase margin is 52.4°. The implemented OTA dissipates only 280 μW from a 0.9-V supply.
Subjects
多位元
連續時間
增加式資料加權平均器
multi-bit
continuous-time
incremental data weighted averaging
Type
thesis
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