A 25-Gbps Dual-Loop Clock and Data Recovery Circuit with Enhanced Data Rate Deviation Tolerance
Date Issued
2014
Date
2014
Author(s)
Liu, Ying-Chen
Abstract
Clock and data recovery (CDR) circuit plays an important role in wireline communication, which can recover data with less jitter and filter channel interference. There’re a few common structures in CDR, phase-locked loop base CDR, phase interpolator based CDR and oversampling CDR.
The thesis proposed a 25-Gb/s dual-loop CDR circuit with enhanced data rate deviation tolerance. The proposed CDR circuit contains two feedback paths, one is proportional path, another one is integral path. Proportional path is identical to the traditional phase interpolator based CDR, which is capable of tracking to instant jitter quickly. The integral path is realized by long term accumulation of the information between clock data, which can extract the frequency information of data, and change the nominal VCO oscillation frequency by adjusting the fractional N phase-locked loop. These two paths together improve the data rate deviation tolerance of CDR.
The measurement results show that the circuit consumes 152 mW under 0.9 V VDD supply. VCO’s phase noise is -100 dBc/Hz at 100-MHz. The phase-locked loop can lock VCO’s oscillation frequency from 23.7 GHz to 27.3 GHz.
Subjects
雙迴圈時脈資料回復電路
相位內插器
鎖相迴路
比例路徑
積分路徑
三角積分調變器
Type
thesis
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