A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
20
Journal Issue
1
Pages
126-134
Date Issued
2012-01
Author(s)
Abstract
This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper. © 2006 IEEE.
Type
journal article