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  4. Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
 
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Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization

Journal
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Journal Volume
2021-November
Date Issued
2021
Author(s)
Wei M.-L
Yayla M
Ho S.-Y
Chen J.-J
Yang C.-L
Amrouch H.
CHIA-LIN YANG  
DOI
10.1109/ICCAD51958.2021.9643463
URI
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85124169911&doi=10.1109%2fICCAD51958.2021.9643463&partnerID=40&md5=d4cfd4e408613f0ac8ed5ccc4e0eecbc
https://scholars.lib.ntu.edu.tw/handle/123456789/607388
Abstract
Spiking Neural Networks (SNNs) are considered the third generation of NNs and can reach similar accuracy as conventional deep NNs, but with a considerable improvement in efficiency. However, to achieve high accuracy, state-of-the-art SNNs employ stochastic spike coding of the inputs, requiring multiple cycles of computation. Because of this and due to the nature of analog computing, it is required to accumulate and hold the charges of multiple cycles, necessitating a large membrane capacitor. This results in high energy, long latency, and expensive area costs, constituting one of the major bottlenecks in analog SNN implementations. Membrane capacitor size determines the precision of the firing time. Hence reducing the capacitor size considerably degrades the inference accuracy. To alleviate this, we focus on bridging the gap between binarized NNs (BNNs) and SNNs. BNNs are rapidly emerging as an attractive alternative for NNs due to their high efficiency and error tolerance. In this work, we evaluate the impact of deploying error-resilient BNNs, i.e. BNNs that have been proactively trained in the presence of errors, on analog implementation of SNNs. We show that for BNNs, the capacitor size and latency can be reduced significantly compared to state-of-the-art SNNs, which employ multi-bit models. Our experiments demonstrate that when error-resilient BNNs are deployed on analog-based SNN accelerator, the size of the membrane capacitor is reduced by 50%, the inference latency is decreased by two orders of magnitude, and energy is reduced by 57% compared to the baseline 4-bit SNN implementation, under minimal accuracy cost. ? 2021 IEEE
Subjects
Errors
Stochastic systems
Binarizations
Energy
Error-resilient
Membrane capacitors
Multiple cycles
Network efficient
Network errors
Neural-networks
State of the art
Third generation
Neural networks
SDGs

[SDGs]SDG7

Type
conference paper

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