A Phase Noise Suppression Technique for PLLs with Ring Oscillators
Date Issued
2014
Date
2014
Author(s)
Cheng, Yi-Han
Abstract
A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillator. The proposed phase-locked loop (PLL) can suppress the noise beyond the PLL loop bandwidth. Fabricated in a 0.18μm CMOS technology, for a 32-kHz input frequency, the 1-GHz PLL with a ring oscillator can generate an output with the phase noise -83 dBc/Hz at a 100-kHz frequency offset, which is more than 10 dB suppression. The clock generator consumes 17.64 mW from a 1.8-V power supply.
Subjects
Frequency synthesizer
phase-locked loop
phase noise
opened-loop delay
closed-loop delay
Type
thesis
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ntu-103-R01943014-1.pdf
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