Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices
Resource
Solid-State Electronics 50 (2006) 109–113
Journal
Solid-State Electronics
Journal Volume
50
Journal Issue
2006
Pages
-
Date Issued
2006
Date
2006
Author(s)
Wei, J.-Y.
Maikap, S.
Lee, M.H.
Lee, C.C.
Liu, C.W.
DOI
246246/2006111501244083
Abstract
Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance–voltage (C–V) characteristics
of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated
results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface
for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals
the Fermi level pinning effect.
Subjects
MOS C–V
Strain
Device simulation
Hole confinement
Pinning effect
Publisher
Taipei:National Taiwan University Dept Chem Engn
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
1534.pdf
Size
22.97 KB
Format
Adobe PDF
Checksum
(MD5):9b5423eb41408fc44db18585b8ffecc9