Analysis and VLSI Architecture Design of Non-Deblocking Loop Filter in HEVC Encoder
Date Issued
2012
Date
2012
Author(s)
Chen, Hsuan-Hung
Abstract
Advanced video applications have an epochal impacts to the history of human visual perception system. Television and communication technology evolve toward more realistic and higher resolution. Many applications, such as high definition TV (HDTV), 3D device and Internet video streaming are developed to fulfill the human desire. However, the massive data size and data loss are still the challenges for these applications. With the advances in video coding technology, the demand of high quality and high definition video encourages the development of next generation video coding standard, High Efficiency Video Coding (HEVC). In 2010, ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) formed a Joint Collaborative Team on Video Coding (JCT-VC) and has began working on the next generation video coding standard HEVC. Many advanced techniques and enhanced coding tools are proposed in HEVC. In this thesis, we analyze and design the algorithm and hardware architecture of non-deblocking loop filter in HEVC.
The non-deblocking loop filter aims to decrease the distortion between original pictures and reconstructed pixels. Sample adaptive offset and adaptive loop filter are two newly adopted tools in HEVC. The non-deblocking loop filter has 5\% coding efficiency gain; nevertheless, the cost is high complexity. In addition, the algorithm of non-deblocking loop filter is not hardware friendly. In order to implement the non-deblocking loop filter on hardware and reduce the complexity, we propose many techniques and hardware architecture. First, we propose many simplifications on SAO and ALF, especially on ALF. We show that much of the hardware resource can be saved yet keeps the video quality and coding performance. Second, we propose unified non-deblocking loop filter flow, two-stage non-deblocking loop filter architecture and LCU level-D data reuse to implement the non-deblocking loop filter on hardware. The proposed hardware architecture reduces 75\% of external memory access bandwidth, 99.9\% of memory usage and more than 40\% of hardware computation resource with only 1.29\% of coding efficiency loss. Based on the proposed algorithm and hardware architecture design, a worldwide first non-deblocking loop filter of HEVC standard hardware with 1.49G pixels/s throughput under the specification Ultra-HD $7680 imes4320$, 30fps is achieved.
Subjects
Video Coding
HEVC
Non-Deblocking Loop Filter
Type
thesis
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