Design and Implementation of the Current Mode Buck Converter with Adaptive Load Transient Enhancement Techniques
Date Issued
2013
Date
2013
Author(s)
Hwang, Bor-Tsang
Abstract
With the evolution of the process, the supply voltage and the signal level decreases. Therefore, fast load transient response to keep output voltage stable and clean becomes very critical for voltage regulators nowadays. Traditional current mode buck converter cannot attain fast transient response due to bandwidth limitations. In this thesis, we propose two new architectures to improve this problem.
The output current slew rate of switching converters is restricted by the inductor. Therefore, the additional current pump is proposed in the literature to provide the insufficient current between the inductor and the output load when loading is changed suddenly. However, this architecture cannot apply to the current mode buck converters directly. In the first chip, we modify this architecture and adopt the adaptive dual current pump technique. Since the output current pump will affect the operation of the original loop, the other current pump is added to make up its impact on the compensation circuit. This technique is implemented with TSMC 0.35μm CMOS process. Measurement results show the recovery time is within 2.8~4 μs. Compared with conventional design, the performance of recovery time is reduced by about 75%. In addition, power conversion efficiency is larger than 82% with load current between 120 mA and 600 mA in proposed architecture. Efficiency degradation is less than 0.3% compared with conventional architecture.
In the second chip, we use the dynamic voltage adjustment of the compensation circuit technique. In current mode control, the voltage of the compensation capacitor needs to be changed according to different load conditions. By adding the inductor current signal to the output of the compensation circuit, the voltage difference of the compensation capacitor at different loads can be reduced. As a result, faster transient response is obtained. This technique is implemented with TSMC 0.25μm CMOS process. Post-layout simulation results show the recovery time is within 3~6 μs. The additional area for implementing this technique is 57.5k μm2, which is much smaller than the previous technique (333k μm2). In addition, power conversion efficiency is larger than 90 % with load current between 100 mA and 500 mA in proposed architecture. Efficiency degradation is less than 0.4% compared with conventional architecture.
Subjects
降壓型轉換器
電流模式控制
暫態響應
電流泵
補償電路
Type
thesis
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