The back-end of layout vs. schematic checker for passive multilayer microwave circuit: schematic mapping using weights
Date Issued
2009
Date
2009
Author(s)
Hsing, Heng-Jui
Abstract
This paper presents an algorithm that can compare the net-lists between schematic and layout of passive microwave multi-layer circuits. Weight vectors that are related to inductance and capacitance of devices connected to a node are defined for node mapping. However, due to the symmetry of microwave circuits, many possible mapping may be found. We then developed a scoring policy to find the most similar mapping. This checker can help designers to verify layout by comparing the net-list from designer’s schematic and layout extracted net-list. This algorithm can also provide missing and extra components in net-list to assist designer to allocate layout errors quickly.
Subjects
Layout
net-list
LVS
Type
thesis
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ntu-98-R96943108-1.pdf
Size
23.32 KB
Format
Adobe PDF
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(MD5):5b993fb7134701f52775ce1fbf6ff911