Analysis of Double-Gate SOI CMOS Devices Using Top N+/Bottom P+ Poly Gate Structure.
Date Issued
2005
Date
2005
Author(s)
Hsu, Chia-Hao
DOI
zh-TW
Abstract
This thesis reports an analysis of double-gate SOI CMOS devices using top N+/Bottom P+ poly gate structure.
In chapter 2, we discuss the threshold voltage model of the normal DG FD SOI PMOS devices without considering gate misalignment effect in different channel length.
In chapter 3,we report an analytical short-channel effect (SCE) transition voltage model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ polysilicon top/bottom gate. The existence of the transition voltage is due to the simultaneous turn-on of the bottom channel in addition to the top channel. As verified by 2D simulation results, this analytical transition voltage model provides a well prediction of the SCE transition voltage behavior of the devices.
In chapter 4, we report an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ poly top/bottom gate considering the threshold/transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the 100nm DG FD SOI NMOS device with the n+/p+ poly top/bottom gate as verified by the 2D simulation results.
Subjects
雙閘式
絕緣體上矽金氧半元件
Double-Gate
soi
Type
thesis