Design and Implementation of CMOS Clock Generation and Clock/Data Recovery Circuits for Wired-line Transceivers
Date Issued
2006
Date
2006
Author(s)
Yang, Rong-Jyi
DOI
en-US
Abstract
With the progress of the CMOS technologies, more and more digital circuits are integrated in a monolithic IC. Thus the commercial products can provide many useful functions with friendly user interfaces for the customers. The digitized multi-media information can be transferred into personal computers or personal digital assistant and shared with friends via the Internet. Thus the demands of the high-speed wired-line interfaces for the handheld devices and the optical communication network for the Internet grow gradually. As the increase of the baud rate for the wired-line communications, the timing margin for the wired-line transceivers is shrinking. Hence the challenge for the clock generation and clock/data recovery circuits also advances.
Delay-locked loops (DLLs) are widely used to solve the issue of clock synchronization due to its un-conditionally stable, faster transient response and less jitter accumulation than the phase-locked loops (PLLs). However, the narrow operating frequency range and no supply noise suppression become the major drawbacks for the DLLs. On the other hand, the clock/data recovery (CDR) circuits play an important pole in the receiver end of the communication systems. The reference-less configuration is better choice than the conventional PLL-based CDR because there is no frequency offset issue between the reference frequency and the input data rate. Nevertheless, the demand for a frequency detector with a wide range of bit rate becomes the bottleneck in the CDR design. Thus the subject of this dissertation is to overcome the defects, to break the limitations and to make a flexible use for the conventional DLLs and the CDR circuits.
The digitally assisted DLL and CDR circuit are introduced first to extend the operating frequency range and lower the conversion gain of the voltage-controlled oscillator / voltage-controlled delay line for the analog operation. The low jitter characteristic of the conventional analog approach is also maintained for the wide range operation. The digitally implemented DLL and CDR circuit are presented then. With the aid of the proposed variable successive approximation register-controlled algorithm, the all-digital DLL can perform the binary search over a wide frequency range without the harmonic locking issue. With the aid of the proposed balanced edge combiner and the lattice delay unit, the DLL outputs a synchronous clock with 50% duty cycle with neither the complementary clocks nor the dual loops architecture. Further, with the aid of the proposed binary phase/frequency detector for the random NRZ data, the digital CDR circuit can perform a binary frequency acquisition and a fast phase tracking. Moreover, several theoretical analyses for the DLLs and CDR circuit are also given to be consistent with the circuit realizations in the dissertation.
Subjects
時脈產生器
延遲鎖定迴路
時脈資料回復電路
頻率偵測器
clock generator
DLL
CDR
PLL
frequency detector
quadricorrelator
Type
thesis
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