Analysis of fringing-electric-field-related capacitance behavior of narrow-channel FD SOI NMOS devices using 3D simulation
Journal
ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages
1376-1379
Date Issued
2007
Author(s)
Abstract
This paper reports the fringing-electric-field-related capacitance behavior of narrow-channel FD SOI NMOS devices using 3D simulation. Based on the results, with a channel width of 0.05 mum, the inner sidewall oxide capacitance (C FIS ) due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V G =0.3V and V D =1V, is the second largest contributor to the gate-source capacitance (C GS )-35%. Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 mum, C FIS cannot be overlooked for modeling gate-source/drain capacitance (C GS /C GD )
SDGs
Type
conference paper