Design of CMOS Delay-Locked Loop for clock generator applications
Date Issued
2005
Date
2005
Author(s)
Hung, Chao-Ching
DOI
en-US
Abstract
With the progress of CMOS technique, the speed performance of VLSI system is increasing rapidly. The complexity of circuits becomes higher and higher. Implementation of system on a chip (SOC) is not a dream anymore. The circuits need a global clock which is generated from a clock generator to synchronize the timing among modules. Besides, for some special applications, systems also need clocks which have the same frequency but difference phase. Meanwhile, in order to ensure that the delays among the clocks are the same, the design of multi-phase clock generator is an important issue. DLLs and PLLs are two kinds of circuit which are widely used to synchronize the system. Traditional DLL is a first order circuit and PLL is a higher order circuit. Compared with higher order circuit, first order circuit is simple and stable. Besides, compared with PLL, the property of low jitter performance of DLL is also one reason why it is more popular.
In chapter one, applications and basic theory are introduced. The parameters of DLL such as bandwidth, jitter performance, and lock time are also elucidated. Besides, different from former theories, latest small signal model and analysis are elucidated as well.
In chapter two, design considerations of DLL are introduced. Some commonly used circuits of the phase detectors, charge pump, and voltage-controlled delay cells are classified.
In chapter three, a calibration circuit which can make the multi-phase clocks of DLL have equal delays are presented. With the variable delay output buffer, we can compensate the delay mismatch due to process variations. Therefore, we can expect that these output clocks of the buffers have equal delay. The proposed architecture have been fabricated in a 0.35-um CMOS process. The whole chip area is 2.1*1.0 mm2 including I/O buffers.
In chapter four, the fabrication of PCB is introduced. The measured waveform and circuit performance are presented as well. When input frequency is 100MHz and operating voltage is 3.3V, the measured pk-pk jitter is 58ps.
In chapter five, we conclude this work.
Subjects
時脈產生器
延遲鎖定迴路
校正
clock generator
delay locked loop
calibration
Type
thesis
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