Low Power Network-on-Chip Switch Architecture Design
Date Issued
2006
Date
2006
Author(s)
Lee, Ju-Yueh
DOI
en-US
Abstract
System-on-a-chip is a trend of modern circuit design. However, with the technology scales down, the inter-communication between IP cores becomes main challenge of SoC design. To overcome the communication problem, Network-on-Chip (NoC) is proposed to provide scalable and reliable on-chip communication. NoC switch (or so-called router) is the most important component of a NoC architecture, and all functions and properties of a NoC is carried out by designing and implementing a switch architecture. In this thesis, a low-power 2-buffer best-effort NoC switch architecture for 2D mesh NoC topology is proposed. By reducing the number of inside buffer and adjusting the buffer size, my work can effectively reduce NoC power consumption. Furthermore, the proposed architecture is free from deadlock since a novel buffering architecture is also proposed in this thesis. Experimental results show that the proposed architecture can save NoC switch power consumption up to 60% comparing with previous switch architecture.
Subjects
低功率
晶片網路
晶片系統
交換器架構
Low Power
Network-on-Chip
System-on-Chip
switch architecture
Type
thesis
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