The Chip design of A 32-b logarithmic number system
Resource
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
4
Pages
167 - 170
Date Issued
1994-06
Date
1994-06
Author(s)
DOI
N/A
Abstract
To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.
Event(s)
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
Other Subjects
Approximation theory; Digital arithmetic; Electric network analysis; Iterative methods; Logic design; Number theory; Table lookup; Digit partition; Hybrid number system; Iterative difference by linear approximation; Logarithmic number system; Microprocessor chips
Type
conference paper
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