Fabrication of Back-Channel-Etched Bottom-Gate Amorphous-InGaZnO Thin Film Transistors

The back-channel-etched (BCE)-type bottom-gate thin film transistor (TFT) structure is the most desired one for the rapidly growing oxide TFT technology due to merits such as simplicity, low cost, ease of device scaling, and compatibility with the existed main-stream a-Si TFT fabrication. Yet until now, the high-etching-selectivity S/D wet etching processes that is required for implementing the BCE-type oxide TFT for large areas has not been successfully demonstrated due to the susceptibility of the amorphous oxides to corrosion by various acids and bases. In this thesis, we have developed such high-selectivity (>100) wet etching processes for widely used TFT electrodes Mo and even Cu, and successfully demonstrated its use in implementing decent BCE bottom-gate amorphous InGaZnO (a-IGZO) TFTs. Such development shall facilitate advances of the oxide TFT technology into the large-area applications and production.
In this thesis, we had also studied the effects of the post-annealing process, which is commonly used in TFT technologies, on using BCE bottom-gate a-IGZO TFTs using Mo S/D electrodes. It was found that as the high-temperature (>240 oC) post-annealing was applied to the TFTs developed in this thesis, the current modulation ability was degraded, and the series resistance increased. Thus we adopted a different annealing process: annealing right after the semiconductor was deposited. Experiment results reveal that TFTs using this annealing process can endure an annealing temperature up to 300 oC and still possess good current modulation ability. Compared to annealing after TFT fabrication at the same annealing temperature (200 oC), this annealing process gains smaller series resistance. Besides, this process yields higher on/off current ratio for TFTs (up to 2.6×109 by the 250 oC annealing process). Finally we applied the wet-etching process and the annealing process to the fabrication of a-IGZO TFTs with Mo/Cu/Mo tri-layer S/D electrodes. These devices show decent TFT performances and high on/off current ratio up to 4.1×109 (by the 250 oC annealing process).