Algorithm and Hardware Architecture Design of Error Concealment and Perceptual Video Coding for Video Communication
Date Issued
2010
Date
2010
Author(s)
Wu, Guan-Lin
Abstract
Video transmission is a challenging work. Many issues, such as bandwidth, heterogeneity, delay, and loss, make the design of video transmission system complicated. From the viewpoint of source coding layer, coding efficiency, error robust and scalability of video coding system are the main challenges for nowadays computation and network environments. This dissertation focuses on the coding efficiency and error robust support issues for video coding system. To increase compression efficiency in the encoder side, a perception-aware video coding system considering human perception is developed. On the other hand, a robust video decoding system including error detection and error concealment is presented to alleviate the erroneous channel effects. Moreover, hardware architecture design of the proposed error concealment algorithms is also concerned in this dissertation because of the tight timing budget for real-time HDTV video processing.
For the proposed perception-aware video coding system, human perceptual consideration is taken into the traditional video coding system to increase the coding efficiency. In image and video coding field, an effective compression algorithm should remove not only the spatial, temporal and statistical redundancy but also the perceptual
redundancy information from the pictures. The proposed perception model helps to achieve better bit allocation for video coding systems by changing quantization parameters at macroblock level. We adopt and combine the structural similarity model, visual attention models, and just-noticeable-distortion model, and contrast sensitivity function to get the weighting of importance of human eye
perception for each macroblock in video frame via a proper fusion algorithm. The proposed algorithms of the model are further developed and modified to be suitable for hardware implementation. Macroblock-based processing with data reuse scheme is used to save the system bandwidth. Moreover, the architecture of parallel processing for each visual model with sharing the on-chip memory and buffers is developed to reduce the chip area. Subjective experiment results show that the proposed model achieves about 7--41% bit-rate saving in the QP range of 24--36 without visual quality degradation. For the hardware implementation of the
proposed evaluation engine, the chip is taped out using 0.18 um technology. The chip size is about 3.3x3.3 mm^2, and the power consumption is 83.9 mW. The processing capability is HDTV720p.
For the erroneous channel effects, we propose a robust video decoding system which including error detection and error concealment schemes for compressed video transmission. The proposed error detection scheme jointly considers spatial and temporal video characteristics. In addition, adaptive threshold value decision scheme is also exploited to let the proposed algorithm suitable for
different video sequences which have different aracteristics. The simulation results show that with the proposed technique, the image quality improvement of 0.5-2.4dB can be achieved. Furthermore, since the proposed method is applied on the decoded frames, it can be used with any coding standard.
Moveover, this dissertation also presents efficient error
concealment algorithms for video bitstream over error-prone channel suffering from damage. An error concealment algorithm for successive frame losses for H.264/AVC bitstream is developed. It estimates the motion field of a lost frame by forward or backward motion projection from a nearly frame which has correct motion field. Experimental results demonstrate that significant quality improvements can be obtained by the proposed algorithm, both objectively and subjectively. On the other hand, for non-successive
frame losses case, a spatial-temporal error concealment is
presented. For spatial error concealment, a mode selection algorithm considering the reuse of intra mode information embedded in bitstream is developed for the adaptation of bilinear and directional interpolation. It suffers only 0.08 dB video quality drop in average but the speedup measured on a general purpose processor is up to 40 times compared with the conventional methods. It is also more suitable for low cost hardware design. For temporal
error concealment, the decoded motion vectors of the neighboring blocks of the corrupted macroblock are reused to provide hints to estimate the motion vector of the corrupted macroblock. Moreover, hardware architecture design and chip implementation of the proposed error concealment algorithm are also presented. For low cost
hardware implementation, a data and computational results reuse scheme of motion vector estimation is proposed and 96% computation and memory bandwidth can be reduced compared with the conventional methods with 0.18 dB quality drop in average. With UMC 90 nm 1P9M process, the proposed error concealment engine can process HDTV1080P 30 frames-per-second video data and the power consumption is 15.77mW
at 125MHz operation frequency. Compared with the previous hardware design of error concealment engine, the proposed design can achieve higher processing capability and up to 1.81 dB gain in PSNR.
In brief, digital video techniques are contributed in two
directions. Coding efficiency of video coding system can be improved based on the cooperation of the traditional video coding scheme and the proposed perception analysis model and hardware engine. Error robust ability of video decoding system is improved based on the proposed error concealment algorithm and hardware engine. We sincerely hope that our research results could make progress for the convenience of human life.
Subjects
error concealment
error detection
video transmission
video hardware
perceptual video coding
Type
thesis
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