A hardware-oriented design for weighted median filters
Resource
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific
Journal
Asian and South Pacific Design Automation Conference, IFIP International Conference on Hardware Description Languages and IFIP International Conference on Very Large Scale Integration, ASP-DAC '95/CHDL '95/VLSI '95
Pages
-
Date Issued
1995-09
Date
1995-09
Author(s)
DOI
N/A
Abstract
In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications.
SDGs
Type
journal article
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