A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
39
Journal Issue
3
Pages
463-468
Date Issued
2004-03
Author(s)
Abstract
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-μm CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.
Subjects
Duty-cycle presetting; Fast locking; Pulsewidth control loop (PWCL); Switched charge pump; Voltage-difference-to-digital converter
SDGs
Other Subjects
CMOS integrated circuits; Electric converters; Phase locked loops; Pulse width modulation; Switching circuits; Timing circuits; Transients; Fast locking control loop; Presettable duty cycle; Pulsewidth control loop; Switched charge pump circuits; Voltage difference to digital converter; Solid state devices
Type
journal article
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