1 V Time-Domain-Based Self-Calibrated Analog-to-Digital Converter with Linear Voltage-to-Delay Circuits in 0.18-um CMOS Technology
Date Issued
2009
Date
2009
Author(s)
Yang, Chung-Hsing
Abstract
This thesis presents two time-domain-based analog-to-digital converters (TD-ADCs) with build-in calibration function. The proposed TD-ADCs utilize dual delay architecture to calibrate the non-idealities. A linear voltage-to-delay circuit is proposed to enhance the linearity of the TD-ADC.oth chips are fabricated in TSMC 0.18 um CMOS process. The first chip consumes 1.6 mA from 1-V supply. The sampling rate is 33 kHz and input common range is from 170 mV to 310 mV. There is no missing code and the area is 1.2 mm by 1.2 mm. The second one consumes 746.3 uA from 1-V supply. The sampling rate is 400 kHz and input common mode range is from 200 mV to 800 mV. With 200 kHz input frequency, the SNR is 41 dB. The area is 1.35 mm by 1.35 mm.
Subjects
analog-to-digital converter
delay
sample and hold
digital-to-analog converter
DAC
successive approximation
linear
Type
thesis
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