總計畫:頻率合成器及傳感介面電路
Date Issued
2005-07-31
Date
2005-07-31
Author(s)
DOI
932215E002031
Abstract
Initially, this project was proposed as a
sub-project of a 3-year NSC integrated project which
aimed to develop a high-performance OFDM
transmitter system for medical instrumentation systems.
This project is responsible for designing a
high-performance frequency synthesizer and key
building blocks for the transducer interface module (for
ultrasound applications). The integrated project was
not recommended by the NSC, and the project became
a one-year project. Therefore, we have focused our
development effort in two key areas: an agile VCO
frequency calibration for a 10-GHz PLL, and a
low-power continuous-time dual-mode delta-sigma
ADC.
In the VCO calibration part, we have proposed a
novel technique that can achieve agile frequency
calibration. This enables a fast PLL frequency
switching, which is important in many wireless
communication applications (e.g. frequency hopping
systems). This proposed technique is realized in TSMC
0.18um CMOS process and the chip is fully functional.
On the second part, we have developed a very
low-power low-voltage continuous-time dual-mode
delta-sigma ADC. Here, we have proposed an opamp
circuit that is suitable for low-power low-voltage
applications. We also proposed a sliding quantizer
technique which can reduce the number of comparators,
and therefore can reduce the power consumption. The
whole ADC is also implemented in TSMC 0.18um
CMOS process. At the time of writing this report, the
chip is under measurement, and initial results suggest
functional work. Detail characterization is still
underway, and more measurement data will be
available later.
Our research work has at least generated at least
an IEE Electronic Letter paper, a domestic journal
paper, and an IEEE international conference paper
(A-SSCC).
Subjects
delta-sigma ADC
data converter
frequency synthesizer
frequency calibration
PLL
phase noise
Publisher
臺北市:國立臺灣大學電子工程學研究所
Type
report
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