Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications
Journal
ISCAS
Pages
3833-3836
Date Issued
2010-05
Author(s)
Abstract
This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at a power supply voltage of 0.5V.
SDGs
Type
conference paper