Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock
Date Issued
2005
Date
2005
Author(s)
Kuo, Qi-Wei
DOI
en-US
Abstract
In this thesis, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18um bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purposes, and use a post-manufacture tunable clock structure that manipulates the clock at post-fabrication stage to compensate for the process dependent violation to the timing. Simulation results have shown that the substrate-bias optimization results in a 37% of power delay improvement and utilization of tunable delay elements achieve 50 ps of almost linear clock tunability.
A phase-locked loop and simple testing circuit also integrate into the chip for timing robustness and measurement purpose. Experiment results show the adder can successfully operate at 2.56GHz working frequency with 1.8V supply voltage.
Subjects
加法器
基板偏壓
adder
substrate bias
PVT variation
Type
thesis
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