Single reference frame multiple current macroblocks scheme for multiple reference frame motion estimation in H.264/AVC
Resource
IEEE Transactions on Circuits and Systems for Video Technology 17 (2): 242-247
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
17
Journal Issue
2
Pages
242-247
Date Issued
2007
Date
2007
Author(s)
Abstract
Due to the multiple reference frame motion estimation (MRF-ME), an H.264/AVC encoder requires ultrahigh memory bandwidth. Conventional multiple reference frames single current macroblock (MRSC) scheme only considers the data reuse within one frame, and requires on-chip memory size and off-chip memory bandwidth in proportional to the reference frame number. In this paper, a single reference frame multiple current macroblocks (SRMC) scheme is presented to further exploit the data reuse at frame level. With frame-level rescheduling of the motion estimation ME procedures in different reference frames, one loaded search window can be utilized by multiple current MBs in different original frames. The demanded on-chip memory size and off-chip memory bandwidth for MRF-ME can thus be reduced to those supporting only one reference frame. Moreover, based on SRMC scheme, an architecture prototype with two-stage mode decision flow is proposed. For HDTV specifications, 62.21 KB (74.8%) of SRAM and 364.3 MB/s (62.6%) of system bandwidth are saved in comparison with the MRSC scheme. © 2007 IEEE.
Subjects
ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; JVT; Motion estimation; Multiple reference frame; VLSI architecture
Other Subjects
Decision flow; Multiple reference frame; VLSI architecture; Bandwidth; Decision theory; Image coding; Search engines; Storage allocation (computer); Motion estimation
Type
journal article
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