An efficient array architecture with data-rings for 3-step hierarchical search block matching algorithm
Resource
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Journal
Circuits and Systems, 1997. ISCAS '97.
Pages
-
Date Issued
1997-06
Date
1997-06
Author(s)
DOI
N/A
Abstract
This paper describes an efficient 9-cells array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify the control scheme and reduce latency, respectively. In addition, we utilize a three-half-search-area scheme to reduce external memory access and interconnection. The results demonstrate that the array architecture with the data-rings gives short latency and low input ports. It also provides a high normalized throughput solution for the 3SHS.
SDGs
Type
journal article
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