Reduced Process Induced Threshold Voltage Variability in Bulk Negative Capacitance Junctionless Transistors
Journal
2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Start Page
1-3
Date Issued
2025-03-09
Author(s)
Abstract
This work provides a comprehensive analysis of threshold voltage () variability () in negative capacitance (NC) junctionless (JL) transistors on silicon-on-insulator (SOI) and bulk substrates through wellcalibrated simulations. Bulk NCJL transistors show improved performance due to a shift in the conduction channel towards the front surface, which improves the gate capacitance () and enhances the negative capacitance in bulk NCJL devices. The results highlight a significant reduction in by , and due to the variations in gate length , silicon film thickness (), equivalent oxide thickness (EOT), channel doping (), and ferroelectric thickness (), respectively. Additionally, the reduced variability further translates to an enhanced noise margin (NM) and improved process-induced NM variations in inverter circuits. The results reported for the first time showcase the superior performance of bulk NCJL designs compared to SOI NCJL transistors.
SDGs
Publisher
IEEE
Type
conference proceedings