Thin film transistors made of nanocrystalline silicon for CMOS on plastic
Journal
Proceedings of SPIE - The International Society for Optical Engineering
Journal Volume
5004
Pages
179-186
Date Issued
2003
Author(s)
Abstract
Our motivation is to realize CMOS on plastic foil. We report the development of thin film transistors (TFTs) made of nanocrystalline silicon (nc-Si:H). nc-Si:H is compatible with present a-Si:H thin film technology. Because of the structural evolution of nc-Si:H with film thickness, it requires extensive experimentation with device geometry. For comparison we fabricate TFTs in (a) conventional coplanar top-gate, top-source/drain geometry and (b) staggered top-gate, bottom source/drain geometry. A seed layer is introduced in the latter case serves to develop the crystallinity of the intrinsic channel layer. While the coplanar geometry provides the shortest carrier path in the most crystalline channel region, the inverted staggered geometry ensures that the active channel is formed in the last-to-grow nc-Si:H layer, and also avoids exposure of the channel to reactive ion etching (RIE). The highest process temperature is 150°C. Both intrinsic and doped nc-Si:H layers are grown by plasma-enhanced chemical vapor deposition with an excitation frequency of 80MHz. Present p-channel TFTs reach a hole field-effect mobility of ~ 0.2 cm2V-1s-1 in the staggered geometry, and an electron field-effect mobility of ~ 40 cm2V-1s-1 in both geometries. These results suggest that directly deposited nc-Si:H is an attractive candidate material for CMOS capable electronics on plastic substrates.
Type
conference paper