High speed memory efficient EBCOT architecture for JPEG2000
Resource
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Journal
2003 International Symposium on Circuits and Systems. ISCAS '03
Pages
-
Date Issued
2003-05
Date
2003-05
Author(s)
DOI
N/A
Abstract
This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000. By parallel coding all the bitplanes, the state variable memory can be eliminated. The proposed architecture can process 50 M coefficients per second at 100 MHz, which can realtime encode 720p resolution of HDTV picture format at 30 fps.
SDGs
Type
journal article
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