A Low Power Sub-range Successive-Approximation ADC
Date Issued
2009
Date
2009
Author(s)
Liu, Yu-Hsun
Abstract
As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving total conversion rate. Then we use overlap action to correct error exist in the MSB comparison. A 12-bit 10MS/s low power consumption Successive-Approximation Analog-to-Digital Converter applied for the Bluetooth system is proposed. This design adopted TSMC 0.13-um 1P8M CMOS process. While the chip operates at sampling rate 10MS/s and Nyquist rate input frequency, the SNDR and SFDR achieve 59.7dB and 69.8dB respectively. The power consumption of core circuit is 3mW. The chip with pads occupies 1.19mm2 and the core area is about 0.096 mm2.
Subjects
SAR ADC
Sub-range
Type
thesis
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