Software workarounds for hardware errors by instruction patch synthesis

Abstract

Due to the ever-increasing complexity of system design, it becomes not uncommon for some design error escaping all verification efforts and settling in final silicon realization. As hardware-based fixing is much more expensive than software-based fixing and manual software-based fixing can be error prone, this thesis proposes a methodology generating software workarounds for erroneous microprocessor designs. The workarounds can be directly applied to assembly code and do not need to modify compiler.This advantage can help the design flow more smooth and no need to iteratively redesign the compiler. In this thesis a generic formulation is introduced based on Skolem and Herbrand function extraction from quantified Boolean formula (QBF) solving; reduction techniques are devised to further enhance practicality. Thereby a program can be recompiled at the assembly code level for correct execution on a buggy microprocessor. Experimental results show the feasibility of the proposed method.