Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup
Journal
Proceedings -Design, Automation and Test in Europe, DATE
Journal Volume
2021-February
Pages
1799-1802
Date Issued
2021
Author(s)
Abstract
An energy-efficient instruction cache lookup technique with low area overheads is proposed. The key concept of this Dynamic Early Tag Lookup (DETL) method is to exploit the presence of instruction fetch-bubble cycles. In a fetch-bubble cycle, the index of the matching cache set can be determined earlier. Hence, the dynamic energy for parallel memory accesses to irrelevant cache banks can be saved. We implemented the proposed DETL algorithm on a 4-way set-associative instruction cache in a RISC-V micro-architecture, and tested its performance using the SPEC CPU2006 benchmark suite. The experiment results showed a 19.38% dynamic power reduction with an area overhead smaller than 0.1 %. ? 2021 EDAA.
Subjects
dynamic early tag lookup
energy-efficient
instruction cache
processor architecture
Benchmarking
Cache memory
Energy efficiency
Benchmark suites
Dynamic power reduction
Energy efficient
Instruction caches
Instruction fetch
Look-up techniques
Micro architectures
Power reductions
Memory architecture
SDGs
Type
conference paper