An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design
Journal
Journal of Circuits, Systems and Computers
Journal Volume
11
Journal Issue
4
Pages
365-375
Date Issued
2002-10
Author(s)
Y. J. Yeh
Abstract
In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.
SDGs
Type
journal article