A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique
Journal
IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages
413-416
Date Issued
2008-11
Author(s)
Abstract
In this paper, a 57.1–59GHz fractional-N frequency synthesizer has been fabricated in 90nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12dB with the same PLL bandwidth. It consumes 89mW from a 1.2V analog supply with output buffers and 16mW from a 1.2V digital supply. The chip occupies 0.86×1.28mm 2 and the measured phase noise at 58.359375GHz with the offset frequency of 2MHz is −95.1dBc/Hz.
SDGs
Type
conference paper