Analysis of Misalignment Effect of DG SOI NMOS Device using Top N+/Bottom P+ Poly Gate Structure
Date Issued
2005
Date
2005
Author(s)
Yang, Chun-Ping
DOI
zh-TW
Abstract
This thesis reports an analysis of gate misalignment effect on capacitance behavior and threshold voltage of double-gate (DG) fully-depleted (FD) silicon on insulator (SOI) NMOS device with N+/P+ poly Top/Bottom gate.
In chapter 1, we make an introduction for SOI device and describe its goods compared with the bulk one.
In chapter 2, we discuss the unique capacitance phenomenon of a 100nm DG FD SOI NMOS device with the N+/P+ poly top/bottom gate.
In chapter 3, we continue the research in chapter 2. Besides, we consider the gate misalignment effect on capacitance behavior and observe the change in it.
In chapter 4, we describe the derivation and verification of threshold voltage of DG FD SOI NMOS device with N+/P+ poly Top/Bottom gate. By using the conformal mapping transformation approach, a model considering the fringing electric field effect in the non-gate overlap region of DG FD SOI NMOS device has been derived to provide an accurate prediction of threshold voltage behavior as verified by the 2D simulation results.
Subjects
閘極不對稱
雙閘
絕緣體上矽
Misalignment Effect
Double Gate(DG)
Silicon on Insulator(SOI)
Type
thesis