Bus Function Models for the Consumer Electronics - Advanced Technology Attachment System
Date Issued
2006
Date
2006
Author(s)
WU, TES-LIN
DOI
en-US
Abstract
As the rapid growth of the complication of SOC, the simulation time spent on verification is getting longer and longer, which results in low efficiency. That is why the traditional method of verification started to be left behind. How to save the time on verification is a very important issue nowadays.
To solve the above problem, this thesis represents a set of Bus Functional Model (BFM) of Consumer Electronics ATA (CE-ATA), and uses tools such as Verilog behavior language and verification language extension. Besides, this thesis also uses several methodologies, transaction based, assertion based, coverage based, to build a verification environment, in order to offer greater help for the chip designer of CE-ATA.
Subjects
配接器
消費性電子
ATA
CE
Type
thesis
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ntu-95-R93943110-1.pdf
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