Power scan: OFT for power switches in VLSI designs

Journal
Proceedings - International Test Conference
Date Issued
2009
Author(s)
Bai, B.-C.
Li, C.-M.
Kifli, A.
Tsai, E.
DOI
URI
URL
Abstract
This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.
SDGs

[SDGs]SDG7

Type
conference paper

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