A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.3-μm CMOS
Journal
IEEE Asian Solid-State Circuit Conference
Pages
91-94
Date Issued
2006-11
Author(s)
Abstract
This paper presents a 50% duty-cycle correction (DCC) circuit. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output signal whose pulse width is controlled by the delay detector to half of the input signal period. Meanwhile, the input phase information is preserved owing to the edge-trigger nature. The circuit is implemented in a TSMC 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing measurement technique is adopted. This circuit operates from 70 MHz to 490 MHz, and accommodates input duty cycles ranging from 10% to 90%. The output signal is corrected to 50% ± 2%. Operated from a 3.3-V supply, the circuit dissipates 8 mA at 490 MHz.
SDGs
Type
conference paper