Physical Design for Reconfigurable Computing System
Date Issued
2004-07-31
Date
2004-07-31
Author(s)
DOI
922215E002018
Abstract
Improving logic capacity by time-sharing,
dynamically reconfigurable FPGAs are employed to
handle designs of high complexity and functionality.
In this report, we model each task as a 3D-box and
deal with the temporal floorplanning/placement
problem for dynamically reconfigurable FPGA
architectures. We present a tree-based formulation,
called T-tree, to represent the spatial and temporal
relations among tasks. Each node in a T-tree has at
most three children which represent the dimensional
relationship among tasks. We present an efficient
packing method and derive the condition to ensure the
satisfaction of precedence constraints which model the
temporal ordering among tasks induced by the
execution of dynamically reconfigurable FPGAs.
Experimental results show that our tree-based
formulation can achieve significantly better solution
quality with less execution time than the most recent
state-of-the-art work.
Subjects
reconfigurable system
reconfigurable computing
physical design
3D
floorplanning
floorplanning
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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