Fast execution for circuit consistency verification
Journal
Integration, the VLSI Journal
Journal Volume
4
Journal Issue
3
Pages
239-262
Date Issued
1986
Author(s)
Abstract
In this paper, a fast solution for circuit consistency verification is investigated. It is an efficient algorithm that is implemented to compare the extracted layout data with the originally designed data. A special partitioning method is guided by the circuit philosophy. This method has two major features over other techniques. First, the average time complexity for verification is only O(M log M), where M is the size of the circuit. Second, it can not only detect the exact error point but also report simultaneously the corresponding correction in the interactive environment. These features will clearly make the design and verification tasks quicker and easier. Experimental results of this verification system show that the circuit comparison can be accomplished by the proposed circuit-based algorithm with nearly linear runtime complexity. © 1986.
Type
journal article