Frame Rate Up-Conversion Algorithm and Hardware Architecture Design for High Definition Liquid Crystal Display
Date Issued
2008
Date
2008
Author(s)
Hsu, Kun-Yen
Abstract
Frame rate up-conversion (FRUC) is applied for video sequences with lower frame rate and to converts the original frame rate to higher one according to different applications. One example application is motion blur reduction on liquid crystal displays (LCD). ecause LCD is a hold-type display, each frame will be displayed and hold in a period of time which is equal to one frame which is different from CRT. Since human eyes have the characteristic to pursuit moving objects with eye-tracking integration smoothly, the artifact named motion blur will be perceived by human eyes. Frame rate up conversion which converts the frame rate to 120Hz, can reduce the motion blur problem effectively. rame rate up conversion is to interpolate the new frames from the original video sequence. The challenge is to deal with the complex motion in a frame, including camera motion and motion of moving objects. There are three kinds of block-based motion compensated interpolating (BMCI) method for frame rate up conversion in the literature. However, the frame interpolation capabilities of these algorithms are only limited to locally translational motion. Some algorithms also consider the camera motion with rotation zoom-in/out can’t be estimated correctly with these simple methods.n this thesis, a new algorithm “Frame Rate Up-Conversion with Global-to-Local Iterative Motion Compensated Interpolation” is proposed. For the global motion compensated interpolation (GMCI), the global motion parameters are estimated with Gradient Descent algorithm, which has high precision. In the next stage, the frame is interpolated with the estimated parameters. After GMCI, the moving blocks are masked and those masked block will be interpolated with BMCI. There are two stages in the proposed BMCI algorithm. In the first stage, those blocks in the moving object will be interpolated. After GMCI and the first stage, the number of rest moving blocks that have not been interpolated becomes small. Because of the high spatial correlation for moving blocks, the motion vectors (MVs) of these blocks are estimated with the predicted MVs belonging to the neighbored interpolated blocks in the second stage.n addition, the frame is interpolated with iterative operations. Through experimental result, the proposed algorithm can provide better visual quality. or high-definition of LCD with the resolution in 1920x1080, the proposed algorithm is too complex for VLSI design. In order to reduce the computation complexity and memory requirement, the memory bandwidth is first analyzed, and several techniques are the proposed to develop a more hardware friendly algorithm. First, in the proposed GME algorithm, the redundant computation of Gradient Descent Algorithm is avoided. The motion parameters of the previous frame are used to estimate global motion parameters with partial pixels and GME is done iteratively in the sub-sampled images. With these techniques, only 1/6 memory bandwidth is required to achieve the similar quality. Furthermore, moving flag masking and probability estimation technique is proposed to decide the interpolation method for each block in advance to reduce the iteration number of the proposed algorithm.n the VLSI hardware design part of this thesis, because the target specification is for frame size 1920x1080 and from 60 fps to 120fps, high memory bandwidth and high complex computing are required. Highly parallel hardware is designed to execute the proposed algorithm in the limited number of cycles. The hardware is accelerated with four times in the proposed GME hardware architecture. In addition the size of local memory is also analyzed and the proposed GMCI hardware architecture can process 16 pixels in parallel in a cycle with the analysis of position for corresponding pixel in the reference frame. The moving block masking and motion compensated interpolation with two stages are also implemented in our proposed hardware architecture.he hardware is implemented with Verilog-HDL and synthesized with SYNOPSYS Design Compiler. Faraday 90 nm cell library is adopted to design the hardware. The total gate count is 1,303 k and the usage of local memory size is 98.92kb. In addition, the power is 64.474mW with 0.9V supply voltage. It is the first hardware architecture for FRUC with GME based on Gradient Descent algorithm which estimates global motion parameters in high precision.
Subjects
Frame rate up-conversion
Type
thesis
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