A Low-Noise Area-Efficient Chopped VCO-based CTDSM for Sensor Applications in 40-nm CMOS
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
52
Journal Issue
10
Date Issued
2017
Author(s)
Abstract
An area-efficient voltage-sensing readout circuit employing chopped voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) is presented in this paper. This VCO-based CTDSM features direct connection to sensors to eliminate pre-amplifier for achieving better hardware efficiency. The VCO is designed as a trans-conductor current-controlled oscillator, which is a fully differential G m stage cascaded with two CCOs, to provide a high-input impedance to sense the voltage signals from sensors. Analysis shows that the main noise and offset contributor is the G m stage. This problem is mitigated by employing choppers at critical location within the circuit. The VCO-based CTDSM is implemented in a 40-nm CMOS process. The power consumption is 17 μW under 1.2V supply. With a 4-mV p (8-mV pp ) input, it achieves 61.85-dB signal-to-noise-and-distortion ratio over a 5-kHz bandwidth and the total harmonic distortion is -70.8 dB. The input-referred noise is 32 nV/√Hz. The chip area is only 0.0145 mm 2 .
SDGs
Type
journal article