Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques
Part Of
APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
Start Page
221
End Page
225
ISBN (of the container)
979-835037877-1
ISBN
979-835037877-1
Date Issued
2024-11-07
Author(s)
DOI
10.1109/APCCAS62602.2024.10808655
Abstract
Interconnect in modern VLSI design has become a dominant factor in circuit timing. Existing buffer insertion approaches suffer from the scalability issue due to the high computational complexity. Repeatedly buffering billions of interconnects to meet timing specifications is not affordable. However, previous timing estimation algorithms at early design stages cannot accurately capture the effects of buffer insertion, which may increase the design iterations to reach timing closure. This paper proposes a two-step delay estimation method for buffered interconnect, combining a heuristic Steiner tree construction and a virtual buffering algorithm. The proposed multi-level cluster tree constructs rectilinear Steiner trees through a recursive clustering mechanism to enhance the accuracy on high-fanout nets. After the routing tree is determined, an equation-based virtual buffering algorithm is proposed to efficiently estimate buffered interconnect delays while keeping a similar quality to the golden buffer insertion algorithm. Experimental results on industrial cases demonstrate the accuracy and efficiency of the proposed approach.
Event(s)
20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024
Publisher
IEEE
Type
conference paper