Design and Implementation of an MC-CDMA Baseband Transceiver for Next-Generation Mobile Communication Systems
Date Issued
2005
Date
2005
Author(s)
Tsai, Pei-Yun
DOI
en-US
Abstract
In this thesis, design and implementation of an MC-CDMA transceiver
for next-generation mobile communication systems are presented.
The proposed system uses the same RF frequency and signal bandwidth
as those of the 3G W-CDMA standards, for its major goal is to increase
the downlink data rate of the current cellular communication system in
urban areas. The system specifications and parameters are chosen
according to the channel models and the highest mobility specified by
3GPP. Since multi-carrier systems are well known to be vulnerable to
synchronization errors, to decrease ICI and MAI resulting from carrier
frequency offset (CFO) and sampling clock offset (SCO), we propose to
jointly estimate the residual CFO and SCO by a weighted least squares
algorithm. Besides, in order to provide accurate channel estimates in
fast-fading channels, a new frequency-domain channel interpolator based
on pilot subcarriers is proposed to track channel variation.
The entire MC-CDMA receiver is integrated and implemented in
0.18 $mu$m CMOS technology. To achieve the target of low power and
small area of mobile units, we have custom-designed bit-reversal
architecture with reduced SRAM requirements. A novel channel interpolation
algorithm is incorporated with much less hardware complexity but more
improved accuracy. In addition, a CORDIC-based TORC equalizer
architecture is implemented to save power and area. Experimental results
of the designed baseband receiver IC demonstrate its superior
system performance up to 21.7 Mbps uncoded data rate.
When running at 5.76 MHz, its power consumption is as
low as 9.9 mW from a supply voltage of 1.1V.
Subjects
多載波
碼域多工
基頻收發機
同步
通道估測
multi-carrier
CDMA
baseband transceiver
synchronization
channel estimation
Type
thesis
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