A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
68
Journal Issue
6
Pages
1837-1841
Date Issued
2021
Author(s)
Abstract
To improve the jitter tolerance (JTOL) of a clock and data recovery (CDR) circuit, a background loop gain controller (BLGC) is presented. This CDR circuit is realized in a 40nm CMOS process. Its active area is 0.0324mm2 and the power consumption is 12.67mW from a 1 V supply. For 1-Gb/s and 3-Gb/s PRBS of 215-1 and the bit error rate < 10-12 , the measured root-mean-square jitter of the retimed data are 12.3ps and 7.74ps, respectively. By using the proposed BLGC, the minimum high-frequency JTOL at 3-Gb/s is improved to 0.68 UIpp. ? 2004-2012 IEEE.
Subjects
background loop gain controller; clock and data recovery; jitter; Jitter tolerance
Other Subjects
Bit error rate; Gain control; Jitter; Timing circuits; 40nm cmos; Active area; Clock and data recovery; High frequency HF; Jitter tolerance; Loop gains; Root mean square jitter; Clock and data recovery circuits (CDR circuits)
Type
journal article