A Virtual Platform for System-on-Chip Design and Verification
Date Issued
2007
Date
2007
Author(s)
Hung, Hsing-Chih
DOI
en-US
Abstract
Electronic System Level (ESL) design methodology is one approach to tackle the modern System-on-Chip (SoC) design complexity. One major aspect is its capability to develop the system model in higher abstraction level and evaluate the system performance for the later hardware and software partition. It enables the seamless hardware and software development at the same time.
In order to ensure a correct hardware and software (HW/SW) co-design, we need to develop a methodology to verify the hardware and software at the same time. Hardware software co-simulation is the most popular approach in HW/SW co-verification. Depending on the design phase, HW/SW co-simulation can be performed at diffident levels of abstraction. In the early design phase, an abstract simulation at the algorithmic or un-partitioned specification level can yield the fastest functional result. However, without the mapping to an architectural executable model (e.g. instruction set architecture), this approach cannot provide reasonable performance estimation of the system. On the other hand, cycle-accurate or nanosecond-accurate model can lead to more accurate timing analysis of the system. However, the corresponding simulation performs so poorly that cannot give the designer any insight into the complete HW/SW interaction. Therefore, we choose the instruction-accurate hardware and software simulation model for the accurate insight to the final system performance.
In this thesis, we develop a virtual platform at the instruction-accurate level. This platform is centered by an abstract modeling of an industrial strength ARM-compatible processor, QuteCore. The surrounding modules, such as DMA controller, bus, arbiter, and memory, are also designed in the abstract computational model. Our platform can achieve fast HW/SW co-simulation speed and at the same time record the performance data for the system-level evaluation and design exploration. We demonstrate the effectiveness of our approach with several examples and the results indicate the tremendous value of the abstract processor modeling. Compared to several previous works, our platform can achieve at least 5 times simulation speedup.
Subjects
電子系統級
軟硬體共同設計
軟硬體共同模擬
軟硬體共同驗證
系統晶片
ESL
SystemC
Electronic System Level
Virtual Platform
Co-simulation
Type
thesis
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