Analysis and Implementation of Accurate 3-D Hierarchical Capacitance Extraction
Date Issued
2011
Date
2011
Author(s)
Dung, Wen-Kang
Abstract
In recent years, the size of chip decreases dramatically due to rapid development of advanced very large scale integration (VLSI) design. With the reduced size of integrated circuit, capacitance extraction has been an important issue while measuring the performance of a circuit. Some simulations like static timing analysis (STA) requires high accuracy of capacitance extraction. Thus how to compute capacitance accurate and fast is necessary for circuit simulation.
In this thesis, we analyze and implement hierarchical capacitance extraction. We first analyze the error estimation while applying hierarchical method. Then we introduce how to build a sparse potential coefficient matrix of self-conductor and mutual conductor separately. Then we let our program to select the minimum side length of the smallest panel spontaneously. An algorithm is proposed to control the accuracy and the run time of simulation result by controlling the error factor.
We will briefly introduce the background of capacitance extraction in Chapter 1. Chapter 2 presents basic concepts of computing capacitance and related algorithms. We analyze the error factors of hierarchical capacitance extraction and the implementation in Chapter 3. Chapter 4 shows some simulation results of our proposed algorithm and the comparison with other algorithms. Finally, we conclude this thesis in Chapter 5.
Subjects
hierarchical capacitance extraction
boundary element method
error estimation
length guard
Type
thesis
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