Waveform approximation technique in the switch-level timing simulator BTS
Resource
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Journal
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Pages
-
Date Issued
1998-06
Date
1998-06
Author(s)
Chang, Molin
Chen, Wang-Jin
Wang, Jyh-Herng
Feng, Wu-Shiung
DOI
N/A
Abstract
In this paper an accurate and efficient switch-level timing simulator is described. The high accuracy is attributed to a new waveform approximation technique, which includes delay estimation and slope estimation. Efficient delay and slope calculations are accomplished through a switch-level simulation instead of using a transistor-level simulation. A new approach for delay estimation is presented, and it models the delay behavior of an RC tree by two equations: a dominant delay equation and an offset delay equation. Both are derived by a special process to fit the surface built by experimental data measured from the actual delay behavior of a CMOS gate. The results show good agreement with SPICE.
Type
journal article
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