Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics
Date Issued
2005
Date
2005
Author(s)
Lin, Yu-Sheng
DOI
zh-TW
Abstract
This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices.
In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses.
In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide.
In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics.
Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages.
Subjects
絕緣體上矽
電容
SOI
high k
capacitance
Type
thesis
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